Structure of a lateral diffusion MOS transistor in widespread use as a power control device

ABSTRACT

There is provided a semiconductor device structured so as to be mounted jointly with other devices on one chip, and capable of controlling a large current in spite of a small device area while having small on-resistance, thereby enabling a high voltage resistance to be obtained. In the case of NLDMOS, the semiconductor device comprises an N well layer, formed on a p-type semiconductor substrate, a P well layer formed in the N well layer, a source electrode formed in a source trench cavity within the P well layer, a gate electrode formed in at least one of gate trench cavities within the P well layer, through the intermediary of an oxide film, and a drain electrode formed in a drain trench cavity within the N well layer, and further, N+ diffused layers are formed, around the source trench cavity, the drain trench cavity, respectively.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device, particularly,to a structure of an LDMOS (Lateral Diffusion MOS) transistor inwidespread use as a power control device for a motor, relay, and soforth, and a process of fabricating the same.

BACKGROUND OF THE INVENTION

A conventional LDMOS device has been in widespread use as an IC devicefor power control that can be mounted jointly with other semiconductordevices on a chip by forming diffused layers in the lateral directionthereof. FIG. 4 shows a basic structure of a conventional n-channelLDMOS by way of example.

The conventional n-channel LDMOS comprises a p-type silicon substrate 1,an N well layer 2 serving as a drain layer of the LDMOS, a P well layer3 serving as a substrate of an N-channel MOS, a LOCOS oxide film 4 of alarge thickness for the purpose of isolation and mitigation of adrain-to-gate electric field, a gate oxide film 5, a gate electrode(polysilicon film) 6, an N + diffused layer 7 for forming a source anddrain, a P + diffused layer 8 for taking out a potential of the P welllayer, an insulating layer (for example, a PSD layer by CVD) 9 forinsulation of a wiring layer from a transistor region, a metalinterconnect layer 10, and a passivation layer 11 for protection of adevice.

The device is operated as follows. A desired voltage is applied to thegate electrode 6, whereupon a current channel layer is induced in asurface region of the P well layer 3 as the substrate, directlyunderneath the gate, thereby causing a current between a drain and asource to flow from the N well layer 2 as a drain region to a sourceregion.

However, advances have recently been made in downsizing and lower powerconsumption of electronic equipment accompanied by rapid progress inminiaturization of semiconductor devices employed by the electronicequipment. In particular, pronounced miniaturization has since been madein common logic MOSLSIs constituting a system LSI. Meanwhile, there havebeen made continued efforts for research and development on downsizingof power devices for controlling relatively large power, such as, forexample, a high voltage resistant device (HV-CMOS), and LDMOS.

Particularly, in the case of the LDMOS, downsizing thereof is essentialin order to mount it jointly with other devices (CMOS logic circuit,bipolar circuit, and so forth) on one chip. Paten Documents 1 , 2, i.e.JP-A 1994-97450 and JP-A 1995-74352, each show a structure for obtaininga high voltage resistant LDMOS transistor while shortening cell pitchesby providing a trench in a gate region or between a gate and drain.

Further, in Paten Document 3, namely, JP-A 1997-139438, there isdescribed a structure wherein a parasitic bipolar transistor is formedtogether with a substrate so as to form a current path when a reversevoltage is applied to a drain, thereby preventing destruction of adevice. Still further, in Paten Document 4, namely, JP-A 1998-294463,there is described a structure of a vertical type device with a currentpath formed in the vertical direction thereof for preventing an electricfield from being concentrated in a square part at the bottom of a gatetrench, thereby preventing leak current.

With a semiconductor device for power control, however, a structure witha large area is still required in effecting power control, which hasbeen the main stumbling block for implementing downsizing of LSI chips.Accordingly, with the conventional LDMOS structure, there has been alimitation to downsizing of a power control system.

SUMMARY OF THE INVENTION

In view of the problem described, the invention has been developed, andit is an object of the invention to provide a novel and improvedsemiconductor device structured so as to be mounted jointly with otherdevices on one chip, and capable of controlling a large current in spiteof a small device area while having small on-resistance, therebyenabling a high voltage resistance to be obtained.

To resolve the problem described, in accordance with a first aspect ofthe invention, there is provided a semiconductor device comprising alayer of a second conductivity, formed on top of a substrate of a firstconductivity, a layer of the first conductivity, formed inside the layerof the second conductivity, a source electrode formed in a trench cavitysurrounded by a first heavily doped region of the second conductivity,inside the layer of the first conductivity, a drain electrode formed ina trench cavity surrounded by a second heavily doped region of thesecond conductivity, inside the layer of the second conductivity, and agate electrode formed in at least one of trench cavities, having asidewall in contact with the first heavily doped region, located on oneedge of the layer of the first conductivity and between the sourceelectrode and the drain electrode, through the intermediary of an oxidefilm covering the inner surface of the trench cavities.

With an LDMOS that is the semiconductor device of the above-describedconfiguration, since current flows along the gate electrode formed inthe respective trench cavities, inside the substrate, it is possible tosecure a channel corresponding to a depth of the trench cavities on theouter side faces of the trench cavities. Furthermore, since a currentbetween a source and drain is dependent on the depth of the trenchcavities, a device area can be developed without taking into account agate length and gate width on a plane as with the case of a conventionalLDMOS transistor, thereby enabling a large current to be controlled.Furthermore, since the source electrode and drain electrode are formedin the trench cavities, respectively, paths of current flowing throughconduction layers in the substrate become shorter, and the current candirectly reach the electrodes, so that on-resistance of the device canbe further reduced. Further, the invention is applicable to either aPMOS or the NMOS.

Herein, a plurality of the trench cavities for the gate electrodes arepreferably disposed in a line in the direction of a channel width. Inthis case, the direction of the channel width refers to a directionnormal, or perpendicular to a direction in which a current flows fromthe drain electrode to the source electrode. Thus, a channel serving asa current path is induced on respective side faces of the plurality ofthe trench cavities, so that larger current can be controlled withoutincreasing the device area. Further, it is desirable to form the trenchcavities for the gate electrodes substantially in the shape of a column,thereby preventing malfunction due to electric field concentration, andso forth.

Further, the trench cavities for the gate electrodes preferably have adepth equal to a depth of the first heavily doped region for reductionof the on-resistance. Furthermore, an impurity concentration of thelayer of the first conductivity is preferably rendered higher than thatof the layer of the second conductivity forming the drain electrode,thereby extending a depletion layer toward the drain side, so that ashort channel effect can be prevented, and a higher voltage resistanceof the drain can be attained.

The structure of the present invention can be applied to a SOI substrateprovided with an insulating oxide film layer formed underneath the layerof the second conductivity type. In this case, the thickness of thelayer of the first conductivity type formed in the layer of the secondconductivity type so as to be smaller than that of the layer of thesecond conductivity type as in the case of a common bulk substrate canbe rendered the same as the thickness of the layer of the secondconductivity type. With the SOI structure adopted, occurrence of aparasitic bipolar transistor can be prevented and parasitic capacitancecan be reduced, thereby preventing malfunction of operation and enablinghigh-speed operation and low current consumption to be achieved, so thatthe device can obtain more excellent characteristics.

Now, in order to obtain the semiconductor device described in theforegoing, there is also provided a process of fabricating asemiconductor device, comprising the steps of forming a layer of asecond conductivity, on top of a substrate of a first conductivity,forming a layer of the first conductivity, inside the layer of thesecond conductivity, forming two trench cavities one of which is locatedon one edge of the layer of the first conductivity, adjacent to thelayer of the second conductivity, inside the layer of the firstconductivity, and forming one trench cavity inside the layer of thesecond conductivity, forming an oxide film on the inner surface of thetrench cavity of the two trench cavities formed inside the layer of thefirst conductivity, formed so as to be closer to the layer of the secondconductivity, embedding electrode metals to serve as a source electrode,drain electrode, and gate electrode, in respective trench cavities,; andforming a first heavily doped region of the second conductivity aroundthe source electrode, so as to be in contact with a sidewall of thetrench cavity for the gate electrode, and forming a second heavily dopedregion of the second conductivity around the drain electrode.

By forming a source trench cavity and gate trench cavities inside thelayer of the first conductivity, and forming a drain trench cavityinside the layer of the second conductivity; the LDMOS semiconductordevice according to the invention can be obtained. Further, since adrain voltage resistance is varied depending on a distance between thesidewall of the respective trench cavities for the gate electrodes andthe second heavily doped region surrounding the trench cavity for thedrain electrode, the distance can be decided upon so as to be able toobtain a desired drain voltage resistance.

The first heavily doped region formed around the trench cavity for thesource electrode is preferably in contact with a part of the sidewall ofeach of the trench cavities for the gate electrodes, however, even ifthere occurs a minute gap in several tenths of a micron therebetween inthe course of fabrication , this will create no problem with theoperation of the transistor.

As described in detail hereinbefore, with the invention, by utilizingthe source trench cavity, gate trench cavities, and drain trench cavitythat are formed in the substrate, the current paths are provided in thesubstrate to thereby perform operation, so that it is possible tocontrol current by virtue of a distance in the direction of the depth ofthe gate trench cavities, thereby enabling the device area on a plane tobe considerably reduced. Thus, the downsizing of the LDMOS can beimplemented, thereby contributing to the downsizing of a semiconductordevice for power control, that is, the downsizing of a system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (a) is a sectional view illustrating a structure of an LDMOSaccording to a first embodiment of the invention;

FIG. 1 (b) is a plan view illustrating the structure of the LDMOSaccording to the first embodiment;

FIG. 2 (a) is a sectional view illustrating a process of fabricating theLDMOS in FIG. 1 (a) according to a second embodiment of the inventionafter the step of ion implantation executed in three stages for forminga P well layer,

FIG. 2 (b) is a sectional view illustrating the process of fabricatingthe LDMOS in FIG. 1 (a) according to the second embodiment of theinvention after the step of forming the P well layer by heat treatment;

FIG. 2 (c) is a sectional view illustrating the process of fabricatingthe LDMOS in FIG. 1 (a) according to the second embodiment of theinvention after the step of forming respective trench cavities;

FIG. 2 (d) is a sectional view illustrating the process of fabricatingthe LDMOS in FIG. 1 (a) according to the second embodiment of theinvention after the step of embedding polysilicon in the respectivetrench cavities;

FIG. 2 (e) is a sectional view illustrating the process of fabricatingthe LDMOS in FIG. 1 (a) according to the second embodiment of theinvention after the step of forming N + diffused layers;

FIG. 2 (f) is a sectional view illustrating the process of fabricatingthe LDMOS in FIG. 1 (a) according to the second embodiment of theinvention after the step of forming a metal interconnect layer andpassivation layer;

FIG. 3 is a sectional view illustrating the structure of an LDMOS formedon a SOI substrate according to a third embodiment of the invention; and

FIG. 4 is a sectional view illustrating the structure of a conventionalLDMOS.

PREFERRED EMBODIMENTS OF THE INVENTION

Preferred embodiments of the invention are described in detailhereinafter with reference to the accompanying drawings. In the presentspecification and the accompanying drawings, constituents havingsubstantially the same function and constitution are denoted by likereference numerals, thereby omitting duplicated description. FirstEmbodiment

FIG. 1 (a) is a sectional view illustrating a trench type LDMOS, thatis, a first embodiment of a semiconductor device according to theinvention. With the present embodiment, an NMOS is described as anexample. The trench type LDMOS comprises an N well layer 102 of a secondconductivity type, formed on a p-type semiconductor substrate 101, thatis, a substrate of a first conductivity type, a P well layer 103 of thefirst conductivity type, formed in the N well layer 102, a sourceelectrode 107 a, a gate electrode 107 b, formed in a source trenchcavity 105 a, a gate trench cavity 105 b, respectively, within the Pwell layer 103, and a drain electrode 107 c formed in a drain trenchcavity 105 a within the N well layer 102.

Further, in order to form the source electrode and the drain electrode,an N + diffused layer 108 a which is a first heavily doped region of thesecond conductivity is formed around the source trench cavity 105 a, andan N + diffused layer 108 c which is a second heavily doped region ofthe second conductivity is formed around the drain trench cavity 105 c.Further, an oxide film 106 to serve as a gate oxide is formed on theinner surface of the gate trench cavity 105 b, and the gate electrode107 b is formed on top of the oxide film 106.

Further, a P + diffused layer 109 which is a heavily doped region of thefirst conductivity type may be formed within the P well layer 103 toenable a potential of the P well layer 103 to be taken out. In addition,a field oxide form 104 for effecting isolation between elements adjacentto each other is formed on the surface of the p-type semiconductorsubstrate 101. The P + diffused layer 109 and the respective electrodesare connected to a metal interconnect layer 112 through respectivecontact holes 111 formed in an intermediate insulating layer 110.

The intermediate insulating layer 110 for insulating the metalinterconnect layer 112 from an underlying element region is formed of aPSG film formed by, for example, CVD process. Further, a passivationlayer 113 is formed on top of the metal interconnect layer 112.

FIG. 1 (a) is a plan view illustrating the trench type LDMOS, that is,the semiconductor device according to the present embodiment of theinvention. In this case, the trench type LDMOS has a configurationhaving three gate trench cavities, and directions 120 of current flowscontrolled by the gate trench cavity at one spot are indicated by thearrows in the figure.

The semiconductor device according to the present embodiment has afeature in that with respect to the gate trench cavity at one spot,conduction occurs, in other word; a current flow is controlled at twospots along the sidewall of the respective gate trench cavities. Thatis, since a current flow channel is induced at two spots, it followsthat current is controlled with a channel width (corresponding to a gatewidth of a conventional MOS transistor) about twice as large as a depthof the gate trench cavity -with respect to one of the gate trenchcavities.

With the present embodiment, the gate trench cavities 105 b are formedat three spots so as to be arranged in a line in the direction of achannel width. With respect to one of the gate trench cavities, acurrent flow occurs at the two spots along the sidewall of the gatetrench cavity, so that if there are three gate trench cavities, acurrent flow will occur at six spots along the respective sidewalls ofthe gate trench cavities. It therefore follows that the more the numberof the trench cavities is, the larger current controlled can be, so thata large current channel can be induced and on resistance can be reducedwithout increasing a device area.

Naturally, however; because there is the need for setting an appropriatespacing between the trench cavities adjacent to each other such thatrespective channels induced along the sidewalls of the trench cavitiesadjacent to each other will not come into contact with each other, thenumber of the trench cavities is set after taking into considerationdesign values such as an electrode width, a current amperage, and so on.

Further, a source and a drain are rendered equivalent in depth to eachother by utilizing the source trench cavity 105 a, and the drain trenchcavity 105 c, respectively, so that the current flows in sidewallregions of the respective gate trench cavities can directly reach theelectrodes without passing through conduction layers in the substrate,along a long distance, respectively, resulting in reduction of theon-resistance. Further, the source trench cavity 105 a and the draintrench cavity 105 c are rendered so as to be a trench substantiallyrectangular in plane shape, respectively, thereby enabling the currentflows along the sidewalls of a plurality of the gate trench cavities tooccur efficiently.

Meanwhile, the gate trench cavities 105 b each are formed in the shapeof a column, and by doing so, it is possible to prevent electric fieldconcentration, thereby enhancing reliability (such as voltageresistance, and so on of the gate insulating film). Further, even if thegate trench cavities 105 b each extend over the N well layer 102, therewill occur no operational problem, however, if the gate trench cavities105 b each are formed at a position inside the P well layer 103, away ata predetermined distance or more from the position of the boundarybetween the P well layer 103 and the N well layer 102, the semiconductordevice according to the present embodiment will not operate as atransistor. Accordingly, the gate trench cavities 105 b each arepreferably located on one edge inside the P well layer 103 therewithin,that is, at a position adjacent to the N well layer 102.

The N + diffused layer 108 a surrounding the source trench cavity 105 ais preferably in contact with the respective sidewalls of the gatetrench cavities 105 b. If the N + diffused layer 108 a is away at adistance from the respective gate trench cavities 105 b, there can be acase where no channel is formed depending on an impurity concentration-of the P well layer 103, and the present semiconductor device does notoperate. Further, in order that a channel is induced throughout a faceon the outer side of the gate trench cavities 105 b, and on-resistanceis reduced to thereby obtain excellent characteristics, the sourcetrench cavity. 105 a is preferably formed such that a depth thereof isslightly shallower that that of the gate trench cavities 105 b while theN + diffused layer 108 c is preferably formed such that a depth thereofis equal to that of the gate trench cavities 105 b.

Because not only the impurity concentration of the P well layer 103 aswell as the N well layer 102 but also a distance between the respectivesidewalls of the gate trench cavities 105 b and the N + diffused layer108 c surrounding the drain trench cavity 105 c are related to a drainvoltage resistance of the device, there is also the need for setting adistance between the gate trench cavities 105 b and the N + diffusedlayer 108 c in such a way as to be able to obtain the drain voltageresistance as desired. Further, by setting the impurity concentration ofthe P well layer 103 higher than that of the N well layer 102, adepletion layer is extended toward the side of the N well layer 102 (tothe drain side), thereby enabling the drain voltage resistance to berendered higher.

Thus, with the present embodiment, since the current flows in the LDMOSmoves in the substrate, along the respective gate electrodes formed inthe gate trench cavities, and the current between the source and thedrain is dependent on a distance in the direction of the depth of thegate trench cavities, the device area can be developed on the basis ofdesign parameters such as only a contact hole diameter, wiring width,and so forth irrespective of a gate width on a plane, and nevertheless,a large current can be controlled Second Embodiment

Now, a process of fabricating the n-channel trench type LDMOS accordingto the first embodiment is described with reference to FIGS. 2 (a)through 2 (f). First, the p-type semiconductor substrate 101 isprepared. For the substrate, use can be made of a silicon substratedoped with, for example, boron and formed such that sheet resistancethereof has a resistance value at about 10 to 50 Ω cm.

Subsequently, desired regions of the p-type semiconductor substrate 101are patterned by use of the well-known photolithography, and thereafter,the N well layer 102 is formed by use of ion implantation techniques andimpurity diffusion techniques. The N well layer 102 has a thickness in arange of about 5 to 10 μm. Since the voltage resistance of the LDMOS isdependent on the impurity concentration of the N well layer 102, theimpurity concentration is set by taking into account a specificationvoltage. The impurity concentration is normally on the order of 1 to 5 E16 cm^(−3.)

Next, a silicon oxide film 201 is formed throughout the surface of thesemiconductor device. A photoresist 202 is formed to a desired thicknesson top of the silicon oxide film 201. After defining an opening inunnecessary regions of the photoresist 202 by application of exposureand development treatments, the silicon oxide film 201 is etched andfurther, ion implantation of, for example, boron ions 203 is executedusing the silicon oxide film 201 and the photoresist 202 as masks. Atthis point in time, a film thickness of the silicon oxide film 201 andthe photoresist 202, respectively, is set such that the boron ions 203will not reach the p-type semiconductor substrate 101 after penetratingthrough the photoresist 202 and the silicon oxide film 201.

Further, with the present embodiment, the boron ion implantation isexecuted by varying ion implantation energies in three stages such thatthe respective energies reach different depths in the substrate. This isdone in order to obtain uniform distribution of impurity concentrationin the P well layer down to respective desired depths in the substrate.Accordingly, variation in the implantation energies is not necessarilylimited to three stages, and the number of times at which ionimplantation is repeated needs to be set to any suitable number so as toobtain uniformity in distribution. As the ion implantation energies inthe three stages, there can be cited, for example, 300 KeV, 800 KeV, and2MeV, respectively. FIG. 2 (a) shows boron distributions 204 in thesubstrate after the ion implantation executed in the three stages,respectively.

Thereafter, the photoresist 202 is removed, and heat treatment(annealing) at a high temperature around 1200° C. is applied, whereuponboron implanted in each of the three stages has substantially uniformdistribution at respective depths in the substrate. A diffused layer ofthe boron becomes the P well layer 103. The P well layer 103 is set tobe shallower in depth than the N well layer 102 so as to be kept insidethe N well layer 102 {refer to FIG. 2 (b)}.

The P well layer 103 has a thickness on the order of 2 to 5 μm, andimpurity concentration thereof, in a range of about 1E17 to 1E18 cm⁻³ isappropriate. Thus, the N well layer 102 is formed on top of the p-typesemiconductor substrate 101, and the P well layer 103 is formed insidethe N well layer 102.

Next, after removal of the silicon oxide film 201, a silicon oxide film104 is again formed to a thickness of several thousands angstromsthroughout the surface of the device. The silicon oxide film 104 isutilized for isolation between elements as well, and is preferably setto have a film thickness sufficient for prevention of occurrence of aparasitic channel between elements adjacent to each other.

Further, it is conceivable to introduce an impurity for channel stop inparasitic channel regions in addition to the silicon oxide film 104 forinsurance purposes. In such a case, boron is used as a dopant. These arethe techniques well- known to those skilled in the art, and addition ofvarious processes and alteration thereof are possible as necessary. As amethod for isolation between elements, use can be made of the LOCOSmethod, STI (Shallow Trench Isolation) method, and so forth.

Further, after sequential execution of a photolithographic step, anoxide film etching step, and a silicon etching step, the source trenchcavity 106 a, gate trench cavity 105 b, and drain trench cavity 105 care formed to respective desired depths in the source region, gateregion and drain region, respectively.

Respective trench cavities for the source trench cavity 106 a and thegate trench cavities 105 b are formed inside the P well layer 103. Asdescribed with reference to the first embodiment, the gate trenchcavities 105 b are preferably formed on one edge of the P well layer103. The trench cavities have a depth short of reaching the bottom ofthe P well layer 103, and the depth can be in a range of about 1 to 3μm. Further, the drain trench cavity 105 c is formed inside the N welllayer 102 {refer to FIG. 2 (c)}.

Furthermore, a drain voltage resistance can be variously set byoptionally setting a distance between the drain trench cavity 105 c andthe P well layer 103. According to a normal specification, the drainvoltage resistance falls in such a very wide range as from about 10 to1000V. Particularly, in the case of raising the voltage resistance ofthe n-channel LDMOS, it is necessary to prevent channel punch-through byextending the depletion layer toward the side of the N well layer 102(toward the drain side). Accordingly, a relation of the impurityconcentration of the P well layer 103 >the impurity concentration of theN well layer 102 is preferably set.

With the present embodiment, the source trench cavity 105 a has anopening substantially rectangular in plane shape, and the gate trenchcavities 105 b are trenches at three spots arranged in a line in thedirection of the electrode width, each having an opening circular inplane shape. The gate trench cavities are preferably formedsubstantially in the shape of a column in order to prevent electricfield concentration, thereby enhancing reliability of the gateinsulating film, such as voltage resistance, and so on. The plurality ofthe gate trench cavities are formed for the reason as described withreference to the first embodiment.

Next, the oxide film 106 to serve as the gate oxide film is formed to athickness in a range of several tens to several hundreds angstroms byuse of the thermal oxidation process. Further, by use ofphotolithography and etching, the gate oxide film 106 is selectivelyleft out only inside the respective gate trench cavities, but is removedin other regions. Subsequently, by use of the CVD process, a polysiliconfilm doped with a dopant, such as phosphorus, arsenic, or the like, inconcentration on the order of 1 to 5E20 cm⁻³, and turned lower inresistance is formed to a thickness several hundreds angstroms on theentire surface in such a way as to be fully embedded inside therespective trench cavities.

At this time, as a constituent material for the respective electrodes,use may be made of a polycide which is a laminated film made ofpolysilicon doped with a dopant for lowering resistance of theelectrodes and a metal with a high melting point (for example, Ti, Co,W, etc.) besides polysilicon.

Next, by use of CMP (Chemical Mechanical Polishing), or etch-backprocess, there is removed the polysilicon film other than that insidethe source trench cavity, the respective gate trench cavities, and thedrain trench cavity. The source electrode 107 a, the gate electrodes 107b, and the drain electrode 107 c are thus formed {refer to FIG. 2 (d)}.

Then, by application of an appropriate thermal diffusion treatment suchas, for example, a process of diffusing an impurity of the polysiliconfilm into surroundings, the N + diffused layer 108 a is formed aroundthe source trench cavity 105 c, and the N + diffused layer 108 c aroundthe drain trench cavity 105 c {refer to FIG. 2 (e)}. It is desirable todesign such that a part of the N + diffused layer 108 a comes intocontact with a part of the sidewall of each of the gate trench cavities105 b at this point in time. Even if a minute gap in several tenths of amicron occurs therebetween, however, this will create no problem withthe operation of the transistor. Respective depths (diffusion spreads)of the N + diffused layer 108 a and the N + diffused layer 108 c maynormally be set to a range of about 0.2 to 1 μm.

Next, there is deposited a CVD film (for example, the PSG film or a BPSGfilm) to serve as the intermediate insulating layer 110 to a thicknessseveral thousands angstroms. Further, in order to connect the sourceelectrode 107 a, the gate electrodes 107 b, and the drain electrode 107c with the wiring, there are formed the contact holes 111, and the metalinterconnect layer 112 (for example, an aluminum film).

Furthermore, as described with reference to the first embodiment, theP + diffused layer 109 may be formed within the P well layer 103 so asto enable the potential of the P well layer 103 to be taken out. In sucha case, the metal interconnect layer 112 is formed on the P + diffusedlayer 109 with the contact hole 111 formed thereon as well. Thereafter,the passivation layer 113 is formed for protection of the device {referto FIG. 2 (f)}. Third Embodiment

FIG. 3 is a sectional view illustrating a trench type LDMOS, that is, athird embodiment of a semiconductor device according to the invention.The third embodiment has a feature that an insulating oxide film layeris formed underneath the layer of the second conductivity type asdescribed with reference to the first embodiment. That is, a SOI(Silicon On Insulator) substrate is used in place of the substrate usedin the case of the first embodiment.

First, there is prepared the SOI substrate obtained by forming apolysilicon oxide film 302 as the insulating oxide film layer, on top ofa p-type semiconductor substrate 301.doped with boron that is asubstrate of a first conductivity type, serving as a support substrate,and further, by forming a silicon layer on the polysilicon oxide film302. As is well known, for the SOI substrate, use may be made of any ofthose prepared by use of a lamination process, a doping process byimplantation of oxygen ions, and so forth.

With the SOI substrate according to the present embodiment, there is noneed for forming a P well layer 103 so as to be shallower in depth thanan N well layer 102, so that the P well layer 103 and the N well layer102 can be formed to the same thickness on the polysilicon oxide film302. Otherwise, the present embodiment is the same in configuration asthe first embodiment, and a process of fabricating the same also issubstantially the same as that according to the second embodiment exceptthat the SOI substrate is used, omitting therefore description thereof.

By adoption of a SOI structure as described, it is possible to preventoccurrence of a problem that a parasitic bipolar transistor {forexample, a transistor formed by the p-type semiconductor substrate 101,the N well layer 102, and the P well layer 103, shown in FIG. 1 (a)} asdescribed in Paten Document 5, namely, JP-A 2002-237591 is activated.Further, with the SOI structure adopted, a parasitic capacitance of thedrain electrode can be reduced, thereby enabling high-speed operationand low current consumption to be achieved.

Having described the preferred embodiments of the invention as abovewith reference to the accompanying drawings, it goes without saying thatthe scope of the invention is not limited thereto. Obviously variousvariations and modifications of the present invention will occur tothose skilled in the art without departing from the spirit and scope ofthe appended claims, and it is our intention that those variations andmodifications naturally be construed within technical bounds of theclaims.

With the above-described embodiments of the invention, description isgiven with reference to the n-channel LDMOS, however, the invention issimilarly applicable to a p-channel LDMOS as well by substituting p-typeelements for all the n-type elements as described.

The invention is applicable to the structure of the LDMOS transistoramong semiconductor devices, and to the process of fabricating the same,and particularly, to the LDMOS transistor capable of controlling a largecurrent while reducing the device area.

1. A semiconductor device comprising: a layer of a second conductivity,formed on top of a substrate of a first conductivity; a layer of thefirst conductivity, formed inside the layer of the second conductivity;a source electrode formed in a trench cavity surrounded by a firstheavily doped region of the second conductivity, inside the layer of thefirst conductivity; a drain electrode formed in a trench cavitysurrounded by a second heavily doped region of the second conductivity,inside the layer of the second conductivity; and a gate electrode formedin at least one of trench cavities, having a sidewall in contact withthe first heavily doped region, located on one edge of the layer of thefirst conductivity and between the source electrode and the drainelectrode, through the intermediary of an oxide film covering the innersurface of the trench cavities.
 2. A semiconductor device comprising: alayer of a second conductivity, formed on top of an insulating oxidefilm layer of a SOI substrate with a substrate of a first conductivitytype, serving as a support substrate thereof; a layer of the firstconductivity, formed so as to be adjacent to the layer of the secondconductivity, and on top of the insulating oxide film layer of the SOIsubstrate; a source electrode formed in a trench cavity surrounded by afirst heavily doped region of the second conductivity, inside the layerof the first conductivity; a drain electrode formed in a trench cavitysurrounded by a second heavily doped region of the second conductivity,inside the layer of the second conductivity; and a gate electrode formedin at least one of trench cavities, having a sidewall in contact withthe first heavily doped region, located on one edge of the layer of thefirst conductivity and between the source electrode and the drainelectrode, through the intermediary of an oxide film covering the innersurface of the trench cavities.
 3. A semiconductor device according toclaim 1, wherein a plurality of the trench cavities for the gateelectrodes are disposed in a line in the direction of a channel width.4. A semiconductor device according to claim 1, wherein the trenchcavities for the gate electrodes are substantially in the shape of acolumn.
 5. A semiconductor device according to claim 1, wherein impurityconcentration of the layer of the first conductivity is higher than thatof the layer of the second conductivity.
 6. A semiconductor deviceaccording to claim 1, wherein a heavily doped region of the firstconductivity type is formed within the layer of the first conductivityto take out a potential of the layer of the first conductivity.
 7. Asemiconductor device according to claim 1, wherein the trench cavitiesfor the gate electrodes have a depth equal to a depth of the firstheavily doped region surrounding the trench cavity for the sourceelectrode.
 8. A process of fabricating a semiconductor device,comprising: forming a layer of a second conductivity, on top of asubstrate of a first conductivity; forming a layer of the firstconductivity, inside the layer of the second conductivity; forming twotrench cavities one of which is located on one edge of the layer of thefirst conductivity, adjacent to the layer of the second conductivity,inside the layer of the first conductivity, and forming one trenchcavity inside the layer of the second conductivity; forming an oxidefilm on the inner surface of the trench cavity of the two trenchcavities formed inside the layer of the first conductivity, formed so asto be closer to the layer of the second conductivity; forming electrodemetals to serve as a gate electrode, source electrode, and drainelectrode, in the trench cavity with the oxide film formed therein, theother trench cavity formed inside the layer of the first conductivity,and the trench cavity formed inside the layer of the secondconductivity, in that order, respectively, and forming a first heavilydoped region of the second conductivity around the source electrode, soas to be in contact with a sidewall of the trench cavity for the gateelectrode, and forming a second heavily doped region of the secondconductivity around the drain electrode.
 9. A process of fabricating asemiconductor device according to claim 8, wherein a plurality of thetrench cavities for the gate electrodes are formed so as to be arrangedin a line in the direction of a channel width.
 10. A process offabricating a semiconductor device according to claim 8, wherein thetrench cavity for the gate electrode is formed substantially in theshape of a column.
 11. A process of fabricating a semiconductor deviceaccording to claim 8, wherein the trench cavity for the gate electrodeis formed such that a depth thereof is equal to a depth of the firstheavily doped region surrounding the trench cavity for the sourceelectrode.
 12. A process of fabricating a semiconductor device accordingto claim 8, wherein a distance between the sidewall of the trench cavityfor the gate electrode and the second heavily doped region of the secondconductivity, surrounding the trench cavity for the drain electrode, isset in such a way as to be able to obtain a drain voltage resistance asdesired.
 13. A process of fabricating a semiconductor device,comprising: forming a layer of a second conductivity, on top of aninsulating oxide film layer of a SOI substrate provided with a substrateof a first conductivity type, serving as a support substrate; forming alayer of the first conductivity on top of the insulating oxide filmlayer of the SOI substrate, so as to be adjacent to the layer of thesecond conductivity, and; forming two trench cavities one of which islocated on one edge of the layer of the first conductivity, adjacent tothe layer of the second conductivity, inside the layer of the firstconductivity, and forming one trench cavity inside the layer of thesecond conductivity; forming an oxide film on the inner surface of thetrench cavity of the two trench cavities formed inside the layer of thefirst conductivity, formed so as to be closer to the layer of the secondconductivity; forming electrode metals to serve as a gate electrode,source electrode, and drain electrode, in the trench cavity with theoxide film formed therein, the other trench cavity formed inside thelayer of the first conductivity, and the trench cavity formed inside thelayer of the second conductivity, in that order, respectively, andforming a first heavily doped region of the second conductivity aroundthe source electrode, so as to be in contact with a sidewall of thetrench cavity for the gate electrode, and forming a second heavily dopedregion of the second conductivity around the drain electrode.
 14. Aprocess of fabricating a semiconductor device according to claim 13,wherein a plurality of the trench cavities for the gate electrodes areformed so as to be arranged in a line in the direction of a channelwidth.
 15. A process of fabricating a semiconductor device according toclaim 13, wherein the trench cavity for the gate electrode is formedsubstantially in the shape of a column.
 16. A process of fabricating asemiconductor device according to claim 13, wherein the layer of thefirst conductivity is formed such that impurity concentration thereof ishigher than that of the layer of the second conductivity.
 17. A processof fabricating a semiconductor device according to claim 13, wherein thetrench cavity for the gate electrode is formed such that a depth thereofis equal to a depth of the first heavily doped region surrounding thetrench cavity for the source electrode.
 18. A process of fabricating asemiconductor device according to claim 13, wherein a distance betweenthe sidewall of the trench cavity for the gate electrode and the secondheavily doped region of the second conductivity, surrounding the trenchcavity for the drain electrode, is set in such a way as to be able toobtain a drain voltage resistance as desired.